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A Practical Guide for SystemVerilog Assertions by Srikanth Vijayaraghavan, Meyyappan Ramanathan (Hardcover, 2005)
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About this product
Product Information
SystemVerilog language consists of three categories of features -- Design, Assertions and Testbench. Assertions add a whole new dimension to the ASIC verification process. Engineers are used to writing testbenches in verilog that help verify their design. Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today. SystemVerilog assertions (SVA) is a declarative language. The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously. This provides the engineers a very strong tool to solve their verification problems. The language is still new and the thinking is very different from the user's perspective when compared to standard verilog language. There is not enough expertise or intellectual property available as of today in the field. While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems. This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.Product Identifiers
PublisherSpringer-Verlag New York Inc.
ISBN-139780387260495
eBay Product ID (ePID)87819821
Product Key Features
Number of Pages334 Pages
Publication NameA Practical Guide for Systemverilog Assertions
LanguageEnglish
SubjectEngineering & Technology, Physics
Publication Year2005
TypeTextbook
Subject AreaElectrical Engineering
AuthorSrikanth Vijayaraghavan, Meyyappan Ramanathan
FormatHardcover
Dimensions
Item Height235 mm
Item Weight740 g
Item Width155 mm
Additional Product Features
Country/Region of ManufactureUnited States
Title_AuthorMeyyappan Ramanathan, Srikanth Vijayaraghavan
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